SN74LVCH16T245DGGR Voltage Level Translator IC

Description

SN74LVCH16T245DGGR: FPGA Spartan-3AN Family 400K Gates 8064 Cells 667MHz 90nm Technology 1.2V 400-Pin F-BGA 

Package: TSSOP-48

Mfr. Part#: SN74LVCH16T245DGGR

Mfr.: TI

Datasheet: (e-mail or chat us for PDF file)

ROHS Status: 

Quality: 100% Original

Warranty: 180 days
 

This 16-bit noninverting bus transceiver uses two separate configurable power-supply rails. The A port is designed to track V_CCA. V_CCA accepts any supply voltage from 1.65 V to 5.5 V. The B port is designed to track V_CCB. V_CCB accepts any supply voltage from 1.65 V to 5.5 V. This allows for universal low-voltage bidirectional translation between any of the 1.8-V, 2.5-V, 3.3-V, and 5-V voltage nodes.

The SN74LVCH16T245 device control pins (1DIR, 2DIR, 1OE, and 2OE) are supplied by V_CCA.

The SN74LVCH16T245 device is designed for asynchronous communication between two data buses. The logic levels of the direction-control (DIR) input and the output-enable (OE) input activate either the B-port outputs or the A-port outputs or place both output ports into the high-impedance mode. The device transmits data from the A bus to the B bus when the B-port outputs are activated, and from the B bus to the A bus when the A-port outputs are activated. The input circuitry on both A and B ports is always active and must have a logic HIGH or LOW level applied to prevent excess I_CC and I_CCZ.

Active bus-hold circuitry holds unused or undriven data inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended. The bus-hold circuitry on the powered-up side always stays active.

This device is fully specified for partial-power-down applications using I_off. The I_off circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

The V_CC isolation feature ensures that if either V_CC input is at GND, then all outputs are in the high-impedance state. To ensure the high-impedance state during power up or power down, OE should be tied to V_CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

Key Features

• Control Inputs V_IH/V_IL Levels are Referenced to 
  V_CCA Voltage
• V_CC Isolation Feature - If Either V_CC Input is at 
  GND, All Outputs are in the High-Impedance State
• Overvoltage-Tolerant Inputs and Outputs Allow
  Mixed-Voltage-Mode Data Communications
• Fully Configurable Dual-Rail Design Allows Each
  Port to Operate Over the Full 1.65 V to 5.5 V 
  Power-Supply Range
• Bus Hold on Data Inputs Eliminates the Need for
  External Pullup and Pulldown Resistors
• I_off Supports Partial-Power-Down Mode Operation
• Latch-Up Performance Exceeds 100 mA Per 
  JESD 78, Class II
• ESD Protection Exceeds JESD 22

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