DRAM Chip DDR4 SDRAM MT40A512M16JY-083E:B

Min.Order: 100
Product origin: Shenzhen, Guangdong, China
Infringement complaint: complaintComplaint
US$ 0.072 ~ 15

Description

Description

MT40A512M16JY-083E:B: DRAM Chip DDR4 SDRAM 8G-Bit 512Mx16 1.2V 96-Pin F-BGA - Trays

Package: FBGA-96

Mfr. Part#: MT40A512M16JY-083E:B

Mfr.:MICRON

Datasheet: (e-mail or chat us for PDF file)

ROHS Status: 

Quality: 100% Original

Warranty: 180 days
 

Product Status
Obsolete
 
Memory Type
Volatile
 
Memory Format
DRAM
 
Technology
SDRAM - DDR4
 
Memory Size
8Gbit
 
Memory Organization
512M x 16
 
Memory Interface
Parallel
 
Clock Frequency
1.2 GHz
 
Write Cycle Time - Word, Page
-
 
Voltage - Supply
1.14V ~ 1.26V
 
Operating Temperature
0°C ~ 95°C (TC)
 
Mounting Type
Surface Mount
 
Package / Case
96-TFBGA
 
Supplier Device Package
96-FBGA (8x14)
 
Base Product Number
MT40A512M16

 

The DDR4 SDRAM is a high-speed dynamic random-access memory internally configured as an eight-bank DRAM for the x16 configuration and as a 16-bank DRAM for the x4 and x8 configurations. The DDR4 SDRAM uses an 8n-prefetch architecture to achieve high-speed operation. The 8n-prefetch architecture is combined with an interface designed to transfer two data words per clock cycle at the I/O pins.A single READ or WRITE operation for the DDR4 SDRAM consists of a single 8n-bit wide, four-clock data transfer at the internal DRAM core and two corresponding n-bit wide, one-half-clock-cycle data transfers at the I/O pins.

Key Features

  • VDD = VDDQ = 1.2V ±60mV
  • VPP = 2.5V, -125mV, +250mV
  • On-die, internal, adjustable VREFDQ generation
  • 1.2V pseudo open-drain I/O
  • TC of 0°C to 95°C
    • 64ms, 8192-cycle refresh at 0°C to 85°C
    • 32ms at 85°C to 95°C
  • 16 internal banks (x4, x8): 4 groups of 4 banks each
  • 8 internal banks (x16): 2 groups of 4 banks each
  • 8n-bit prefetch architecture
  • Programmable data strobe preambles
  • Data strobe preamble training
  • Command/Address latency (CAL)
  • Multipurpose register READ and WRITE capability
  • Write and read leveling
  • Self refresh mode
  • Low-power auto self refresh (LPASR)
  • Temperature controlled refresh (TCR)
  • Fine granularity refresh
  • Self refresh abort
  • Maximum power saving
  • Output driver calibration
  • Nominal, park, and dynamic on-die termination (ODT)
  • Data bus inversion (DBI) for data bus
  • Command/Address (CA) parity
  • Databus write cyclic redundancy check (CRC)
  • Per-DRAM addressability
  • Connectivity test (x16)
  • JEDEC JESD-79-4 compliant
  • sPPR and hPPR capability

 

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Why choosing us

  • Located in Shenzhen, the electronic market center of China.
  • 100% guarantee components quality: Genuine Original.
  • Sufficient stock on your urgent demand.
  • Sophisticated colleagues help you solve problems to reduce your risk with on-demand manufacturing
  • Faster shipment: In stock components can ship the same day .
  • 24 Hours service 

 

Notice:

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  2. You can contact sales person to apply for a better price.
  3.  For more products, Pls do not hesitate to contact our Sales team.   
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