Mounting Style: | SMD/SMT | |
Package / Case: | PBGA-324 | |
Series: | AM3356 | |
Core: | ARM Cortex A8 | |
Number of Cores: | 1 Core | |
Data Bus Width: | 32 bit | |
Maximum Clock Frequency: | 800 MHz | |
L1 Cache Instruction Memory: | 32 kB | |
L1 Cache Data Memory: | 32 kB | |
Operating Supply Voltage: | 1.26 V | |
Minimum Operating Temperature: | - 40 C | |
Maximum Operating Temperature: | + 105 C | |
Packaging: | Tray | |
Brand: | Texas Instruments | |
Data RAM Size: | 64 kB, 64 kB | |
Data ROM Size: | 176 kB | |
Development Kit: | TMDXEVM3358 | |
I/O Voltage: | 1.8 V, 3.3 V | |
Interface Type: | CAN, Ethernet, I2C, SPI, UART, USB | |
L2 Cache Instruction / Data Memory: | 256 kB | |
Memory Type: | L1/L2/L2 Cache, RAM, ROM | |
Moisture Sensitive: | Yes | |
Number of Timers/Counters: | 8 Timer | |
Processor Series: | Sitara | |
Product Type: | Microprocessors - MPU | |
Factory Pack Quantity: | 126 | |
Subcategory: | Microprocessors - MPU | |
Tradename: | Sitara | |
Watchdog Timers: | Watchdog Timer | |
Unit Weight: | 0.060453 oz |
1.2 Applications • Gaming Peripherals • Home and Industrial Automation • Consumer Medical Appliances • Printers • Smart Toll Systems • Connected Vending Machines • Weighing Scales • Educational Consoles • Advanced Toys (1) For more information, see Section 9, Mechanical, Packaging, and Orderable Information. 1.3 Description The AM335x microprocessors, based on the ARM Cortex-A8 processor, are enhanced with image, graphics processing, peripherals and industrial interface options such as EtherCAT and PROFIBUS. The devices support high-level operating systems (HLOS). Processor SDK Linux® and TI-RTOS are available free of charge from TI. The AM335x microprocessor contains the subsystems shown in the Functional Block Diagram and a brief description of each follows: The contains the subsystems shown in the Functional Block Diagram and a brief description of each follows: The microprocessor unit (MPU) subsystem is based on the ARM Cortex-A8 processor and the PowerVR SGX™ Graphics Accelerator subsystem provides 3D graphics acceleration to support display and gaming effects. The PRU-ICSS is separate from the ARM core, allowing independent operation and clocking for greater efficiency and flexibility. The PRU-ICSS enables additional peripheral interfaces and real-time protocols such as EtherCAT, PROFINET, EtherNet/IP, PROFIBUS, Ethernet Powerlink, Sercos, and others. Additionally, the programmable nature of the PRU-ICSS, along with its access to pins, events and all system-on-chip (SoC) resources, provides flexibility in implementing fast, real-time responses, specialized data handling operations, custom peripheral interfaces, and in offloading tasks from the other processor cores of SoC.