Ti Ds90ub941asrtdrq1 Battery Power Charger Control Management Integrated Circuit IC Voltage Monitor Protector Electronic Components Chip

Quality information

Packaging information

• AEC-Q100 qualified for automotive applications with the following results:
  • Device temperature grade 2: −40ºC to +105ºC ambient operating temperature
• Supports pixel clock frequency up to 210 MHz for 3K (2880x1620) at 30Hz, QXGA (2048x1536), 2K (2880x1080), WUXGA (1920x1200), or 1080p60 (1920x1080) resolutions with 24-bit color depth
• MIPI D-PHY / Display Serial Interface (DSI) receiver provides a high-bandwidth interface to video processor or FPGA
  • Dual DSI input ports with up to 4 data lanes each
  • Up to 1.5 Gbps per lane
  • Superframe with symmetric and asymmetric unpacking capability
  • ECC and CRC generation
  • Virtual channel capability
• Single and dual FPD-Link III outputs
  • Single link: up to 105MHz pixel clock
  • Dual link: up to 210MHz pixel clock

• Functional Safety-Capable

  • Documentation available to aid ISO 26262 system design

• Symmetric and asymmetric video splitting

The DS90UB941AS-Q1 is a dual DSI to FPD-Link III bridge serializer designed for automotive infotainment applications. When paired with an FPD-Link III DS90UB940N-Q1, DS90UB948-Q1, DS90UB924-Q1, DS90UB926Q-Q1 or DS90UB928Q-Q1 deserializer, the DS90UB941AS-Q1 can supply 1- or 2-lane high-speed serial streams over cost-effective, 50 Ω, single-ended coaxial cables or over 100 Ω, differential shielded twisted-pair (STP) and shielded twisted-quad (STQ) cables. In response to the rise in number and variance of displays in infotainment systems, the DS90UB941AS-Q1 can support symmetric and asymmetric splitting.

The DS90UB941AS-Q1 can consolidate video data over two differential pairs to simplify system design and decrease the interconnect size and weight of the application.

The FPD-Link III interface supports video and audio data transmission and full duplex control, including I2C communication and up to eight I2S audio channels over the same high-speed serial link. EMI is minimized by the use of low voltage differential signaling, data scrambling, and randomization.