B5116ECMDXGJD-U DRAM Chip DDR3L SDRAM 8Gbit 512M x 16 1.35V 96-Pin FBGA IC

Specifications
• Density: 8G bits
• Organization 64Mwords x 16bits x 8banks
• Package 96-ball FBGA Lead-free (RoHS compliant) and Halogen-free
• Power supply: 1.35V (Typ) VDD, VDDQ = 1.283V to 1.45V Backward compatible for VDD, VDDQ=1.5V 0.075V
• Data rate 1866Mbps / 1600Mbps (max.)
• 2KB page size Row address: A0 to A15 Column address: A0 to A9
• Eight internal banks for concurrent operation
• Burst lengths (BL): 8 and 4 with Burst Chop (BC)
• Burst type (BT): Sequential (8, 4 with BC) Interleave (8, 4 with BC)
• Programmable /CAS (Read) Latency (CL)
• Programmable /CAS Write Latency (CWL)
• Precharge: auto precharge option for each burst access
• Driver strength: RZQ/7, RZQ/6 (RZQ = 240Ω)
• Refresh: auto-refresh, self-refresh


Features
• Double-data-rate architecture: two data transfers per clock cycle
• The high-speed data transfer is realized by the 8 bits prefetch pipelined architecture
• Bi-directional differential data strobe (DQS and /DQS) is transmitted/received with data for capturing data at the receiver
• DQS is edge-aligned with data for READs; centeraligned with data for WRITEs
• Differential clock inputs (CK and /CK)
• DLL aligns DQ and DQS transitions with CK transitions
• Commands entered on each positive CK edge; data and data mask referenced to both edges of DQS
• Data mask (DM) for write data
• Posted /CAS by programmable additive latency for better command and data bus efficiency
• On-Die Termination (ODT) for better signal quality Synchronous ODT Dynamic ODT Asynchronous ODT
• Multi Purpose Register (MPR) for pre-defined pattern read out
• ZQ calibration for DQ drive and ODT
• Automatic self refresh (ASR)
• /RESET pin for Power-up sequence and reset function
• SRT range: Normal/extended
• Programmable Output driver impedance contro