Optical Fiber RoHS Compliant 100GB/S Cfp4 Lr4 10km Optical Receiver

Min.Order: 1

Product origin: Jiaxing, Zhejiang, China

Infringement complaint:

Complaint

US$ 1 ~ 99

Description

Product Features

Commerical:0 to 70 °C

Applications

Standards

Absolute Maximum Ratings

Note: Stress in excess of the maximum absolute ratings can cause permanent damage to the transceiver.

Electrical Characteristics
(Tested under recommended operating conditions,unless otherwise noted)

Parameter		Symbol		Unit	Min	Typ	Max	Notes
Voltage Supply Electrical Characteristics
Supply Current	Tx Section		Icc	A			0.9	1
Supply Current	Rx Section		Icc	A			0.9	1
Power Supply Noise			Vrip				2% DC	1MHz
Power Supply Noise			Vrip				3% 1	10MHz
Total Dissipation Power			Pw	W			8
Low Power Mode Dissipation			Plow	W			2
Inrush Current	Class1	and	I-inrush	mA/usec			100
Turn-off Current	Class2	and	I-turnoff	mA/usec	-100
Inrush Current	Class3	and	I-inrush	mA/usec			200
Turn-off Current	Class4	and	I-turnoff	mA/usec	-200
Different Signal Electrical Characteristics
Single Ended Data Input Swing				mV	20		525
Single Ended Data Output Swing				mV	180		385
Differential Signal Output Resistance				Ω	80		120
Differential Signal Input Resistance				Ω	80		120
3.3V LVCMOS Electrical Characteristics
Input High Voltage			3.3VIH	V	2.0		Vcc+0.3
Input Low Voltage			3.3VIL	V	-0.3		0.8
Input Leakage Current			3.3IIN	uA	-10		+10
Output HighVoltage (IOH=100uA)			3.3VOH	V	Vcc-0.2
Output Low Voltage (IOL=100uA)			3.3VOL	V			0.2
Minimum Pulse Width of Control Pin Signal			t_CNTL	us	100
1.2V LVCMOS Electrical Characteristics
Input High Voltage			1.2VIH	V	0.84		1.5
Input Low Voltage			1.2VIL V	0.3	1.2VIL V		0.36
Input Leakage Current			1.2IIN	uA	-100		+100

High Speed Electrical Characteristics

Parameter	Symbol	Unit	Min.	Max.	Notes
Impedance	Zd	Ω	90	110
Frequency		MHz	161.1328125		1/64 of electrical lane rate
Frequency Stability	△f	ppm	-100	100	For Ethernet
Frequency Stability	△f	ppm	-20	20	For Telecom
Differential Voltage	VDIFF	mV	400	900	Peak to Peak Differential
Common mode noise (rms)		mV		17.5
RMS jitter		ps		10	Random Jitter Over frequency band of 10KHZ<f<10MHZ
Clock Duty Cycle		%	40	60

Optical Characteristics
(Tested under recommended operating conditions,unless otherwise noted)

Parameter	Symbol	Unit	Min	Typ	Max	Notes
Optical Receiver Characteristics
Receive Rate for Each Lane		Gbps		25.78125	27.9525
Overload Input Optical Power	Pmax	dBm	5.5			3
Average Receive Power for Each Lane	Pin	dBm	-8.6		3	4
Receive Power In OMA for Each Lane	PinOMA	dBm			3
Difference in Receive Power in OMA between Any Two Lanes		dBm
Receiver Sensitivity in OMA for Each Lane	SOMA	dBm			-8.6	5
Stressed Receiver Sensitivity in OMA for Each Lane		dBm			-6.8	6,7

The supply current includes CFP4 module's supply current and test board workingcurrent.
Average launch power, each lane (min) is informative for 100GBase-LR4, not the principal indicator of signal strength.
The receiver shall be able to tolerate , without damage, continuous exposure to an optical input signal having this average power level
Average receive power, each lane (min) is informative and not the principal indicator

of signal strength. A received power below this value cannot be compliant; however, a value above this does not ensure compliance

Hardware Control Pins
The CFP4 Module support real-time control functions via hardware pins, listed in the following

Pin	Symbol	Description	I/O	Logic	H	L	Pull-up/down
14	MOD_LOPWR	Module Low Power Mode	I	3.3V LVCMOS Low Power Enable Pull-Up	Low Power	Enable	Pull-Up Note1
16	MOD_RSTn	Module Reset(Invert)	I	3.3V LVCMOS	Enable	Reset	Pull-Down Note2

The CFP4 Module supports alarm hardware pins listed in the following

1:.Pull-Down resistor (<100Ohm) is located within the CFP4 module. Pull-up should be located on the host

The CFP4 Module supports alarm, control and monitor functions via an MDIO bus. The CFP4 MDIO pins are listed in the following:

Pin	Symbol	Description		I/O	Logic		H	L	Pull-up/down
13	GLB-ALRM n	Global Alarm		I	3.3V LVCMOS		OK	Alarm
18	MDIO	Management interface bidirectional data		I/O	1.2V	LVCMOS
17	MDC	Management interface clock input		I	1.2V	LVCMOS
19	PRTADR0	MDIO physical address bit 0	port	I	1.2V	LVCMOS	Per MDIO
20	PRTADR1	MDIO physical address bit 1	port	I	1.2V	LVCMOS
21	PRTADR2	MDIO physical address bit 2	port	I	1.2V	LVCMOS

Hardware Signaling Pin Timing Requirements
Timing Parameters for CFP4 hardware Signal Pins are listed in the following:

Parameter	Symbol	Unit	Min.	Max.	Notes
Hardware MOD_LOPWR assert	t_MOD_LOPWR_assert	ms		1
Hardware MOD_LOPWR deassert	t_MOD_LOPWR_deassert	s		60	Stored in NVR register 8072h
Management interface clock period	t_prd	ns	250		MDC is 4 MHz rate or less
Host MDIO setup time	t_setup	ns	10
Host MDIO hold time	t_hold	ns	10
CFP4 MDIO delay time	t_delay	ns	0	175
GLB_ALRM assert time	GLB_ALRMn_assert	ms		150	A logic "OR" of associated MDIO alarm and status registers
GLB_ALRM deassert time	GLB_ALRMn_deassert	ms		150	A logic "OR" of associated MDIO alarm and status registers
Minimum pulse width of control	t_CNTL	μs	100

pin signal
Initialization time from reset	t_initialize	s	2.5
TX_Disable assert time	t_deassert	μs	100	Transmitter disable, application specific
TX_Disable deassert time1	t_assert	ms	5	Time from Tx Disable pin deasserted until CFP4 module enters the Tx-turn-on state Stored in NVR register 8073h
RX_LOS assert time	t_loss_assert	μs	100	From occurrence of loss of signal to assertion of RX_LOS
RX_LOS deassert time	t_loss_deassert	μs	100	From occurrence of return of signal to deassert of RX_LOS

CFP4 Lane Assignment