MIPI-DSI interface
DSI-CLK Lanes
DSI-CLK+/- lanes can be driven into three different power modes: Low Power Mode (LPM LP-11), Ultra Low PowerMode (ULPM) or High Speed Clock Mode (HSCM).Clock lanes are in a single end mode (LP = Low Power) when there is entering or leaving Low Power Mode(LPM) orUltra Low Power Mode (ULPM).
Clock lanes are in the single end mode (LP = Low Power) when there is entering in or leaving out High Speed Clock
Mode(HSCM).
These entering and leaving protocols are using clock lanes in the single end mode to generate an entering orleaving sequences
The principal flow chart of the different clock lanes power modes is illustrated below.
DSI-CLK+/- lanes can be driven to the Low Power Mode(LMP),when DSI-CLK lanes are entering LP-11 State Code
in three different ways:After SW Reset,HW Reset or Power On Sequence->LP-11After DSLCLK+/- lanes are leaving Ultra Low Power Mode (ULPM,LP-00 State Code)=>LP10=>LP-11(LPM)This sequence is illustrated below.
Reliability Note 1: Ta is the ambient temperature of samples.
Note 2: Ts is the temperature of panel's surface.
Note 3: In the standard condition, there shall be no practical problem that may affect the
display function. After the reliability test, the product only guarantees operation,
but don't guarantee all of the cosmetic specification.
Note 4: Before cosmetic and function test, the product must have enough recovery time,
at least 2 hours at room temperature.
Complaint
